1. Field of the Invention
The present invention relates to the structure of a semiconductor device such as a MOS device, and a method for manufacturing the same.
2. Description of the Background Art
The structure, in particular, the gate dimension of a MOS device which is a semiconductor device having a MOS transistor has been reduced in order to get higher speed and greater driving ability. However, as the gate dimension is reduced more, wiring delay is increased due to the parasitic effects of a wiring (such as a wiring capacity or the like). For this reason, it has been desired that the driving ability of the device can be enhanced more.
FIG. 25 is a sectional view showing the structure of a MOS device according to the prior art. As an example, an N type MOS transistor will be described below. In FIG. 25, 1 designates a silicon substrate, 1A designates a P type well region formed on the upper layer portion of the silicon substrate 1, 2 designates a thick oxide film for isolation between elements (hereinafter referred to as a field oxide film), 3 designates a channel region, 4 designates a gate oxide film formed on the channel region 3, 5C designates a gate electrode formed on the gate oxide film 4, 6C designates an N type drain region which includes N type impurities, and 7C designates an N type source region which includes the N type impurities. The drain region 6C and the source region 7C are formed with the channel region 3 held therebetween.
In FIG. 25, 8 designates a layer insulating film formed on the overall surface, 9 designates a contact hole for connection of a wiring layer to the drain or source region which is selectively formed on the layer insulating film 8, 10 designates an aluminum wiring layer which fills the contact hole 9, and 11 designates a passivation film for device surface protection which covers the layer insulating film 8 and the aluminum wiring layer 10.
FIG. 26 is a plan view showing the structure of the MOS device according to the prior art. For convenience of explanation, the layer insulating film 8 and the passivation film 11 shown in FIG. 25 are omitted. L designates a gate length and W4 designates a gate width of a source-drain region. FIG. 25 shows a D--D section of FIG. 26. In FIG. 26, a wiring layer 50 is electrically connected to the gate electrode 5C through a contact hole 51 formed on the gate electrode 5C.
The MOS device according to the prior art has the structures shown in FIGS. 25 and 26. The gate length L has been reduced in order to enhance the driving ability. However, the reduction of the gate length L has limitations in respect of the source-drain pressure resistance if the well concentrations are the same.
For this reason, the increase in the gate width W is the only way to enhance the current driving ability still more. However, when the gate width W is made greater, the size (chip size) of the semiconductor device is increased so that integration is deteriorated. Consequently, reduction cannot be obtained.